Hardware co-simulation refers to a technique for testing circuit designs, or portions thereof, implemented within an integrated circuit such as a programmable logic device (PLD). Typically, a PLD is utilized as a test platform within which the circuit design, or some portion thereof, is implemented. For example, the PLD may be mounted on a circuit board that is communicatively linked with a host computing system through a communication channel. The host computing system (host) can execute simulation software that can interact with the PLD and the circuit design, referred to as the “design under test” or “DUT,” implemented within the PLD.
To facilitate hardware co-simulation, a hardware co-simulation interface (HWCIF) is implemented within the PLD in conjunction with the DUT. The HWCIF supports interaction between the host and the DUT. Typically, the host communicates with the DUT through a memory map. The memory map associates each input/output port of the DUT with a particular memory address. Data can be provided to a selected port of the DUT by writing to the memory address of the memory map that corresponds to the selected port. Data can be obtained from a selected port of the DUT by reading from the memory address of the memory map that corresponds to the selected port.
The host can initiate a read or a write operation with respect to the DUT by issuing commands to the PLD via the communication channel. The HWCIF can translate the received commands into appropriate operations that are understandable by the DUT. The HWCIF further can perform the inverse function with respect to data obtained from the DUT to be provided back to the host.
Modern computer systems and PLDs typically offer sufficient computing power to quickly and efficiently perform their roles within the context of hardware co-simulation. The amount of data that is transferred between the host and the PLD, however, can be significant. Implementing a communication protocol over the communication channel can introduce further overhead. For example, processes such as setting up and tearing down data transfers, packetization, routing, synchronization, and the like may require further time and require additional data to be exchanged over the communication channel apart from the actual test data and test results. It is often the case that the communication channel, suffering from limited bandwidth, latency, congestion, or the like, is the bottleneck within the hardware co-simulation system.